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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Features
10 Mbits/s Transceiver
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100 Mbits/s FX Transceiver
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Compatible with IEEE 802.3u 100Base-FX standard. Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL (PECL) data. Fiber mode automatically configures port: -- Pin or register selectable -- Disables autonegotiation and 10Base-T. -- Enables 100Base-FX remote fault signaling. -- Disables MLT-3 encoder/decoder. -- Disables scrambler/descrambler.
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DSP based. Compatible with IEEE * 802.3 10Base-T standard for twisted-pair cable. Half- and full-duplex operations. Autopolarity detection and correction. Adjustable squelch level for extended wire-length capability (2 levels). Interfaces with IEEE 802.3u media independent interface (MII) or a serial 10 Mbits/s 7-pin interface. On-chip filtering eliminates the need for external filters.
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General
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100 Mbits/s Transceiver
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Autonegotiation and management: -- Fast link pulse (FLP) burst generator. -- Arbitration function. -- Accepts preamble suppression. -- Operates up to 12.5 MHz. Supports the MII station management protocol and frame format (clause 22): basic and extended register set. Supports next page. Provides status signals: receive activity, transmit activity, full duplex, collision/jabber, link integrity, and speed indication. Powerdown mode for 10 Mbits/s and 100 Mbits/s . Loopback for 10 Mbits/s and 100 Mbits/s . Proprietary Low Power Mode (Nowire mode) for saving power when there is not activity on Receive side. 0.25 m low-power CMOS technology. Single 3.3 V power supply operation. 25 MHz XTAL oscillator input or 25 MHz/50 MHz/ 125 MHz clock input. Compatible with RMII (standard version) and SMII (standard version).
Compatible with IEEE 802.3u MII (clause 22), PCS/PMA (clause 24), PMD (clause 25), MII management, and autonegotiation (clause 28) specifications. Selectable 5-bit code-group (PDT/PDR interface) or 4-bit data nibbles (MII interface) input/output. Full- or half-duplex operations. Optional carrier integrity monitor (CIM). Selectable carrier sense signal generation (MCRS) asserted during either transmission or reception in half duplex (MCRS asserted during reception only in full duplex). Adaptive equalization and baseline wander correction. On-chip filtering eliminates the need for external filters.
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* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
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Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Table of Contents
Contents Page
Features .................................................................................................................................................................... 1 10 Mbits/s Transceiver ............................................................................................................................................ 1 100 Mbits/s Transceiver .......................................................................................................................................... 1 100 Mbits/s FX Transceiver ..................................................................................................................................... 1 General ................................................................................................................................................................... 1 Description ................................................................................................................................................................ 4 Functional Block Diagram .......................................................................................................................................4 Macrocell I/Os ......................................................................................................................................................... 5 Signal Information...................................................................................................................................................... 6 Signal Descriptions ................................................................................................................................................. 6 MII Station Management .........................................................................................................................................13 Basic Operation ....................................................................................................................................................13 MII Interface Design ................................................................................................................................................14 Absolute Maximum Ratings.....................................................................................................................................14 Electrical Characteristics .........................................................................................................................................15 Register Information ................................................................................................................................................19 Register Descriptions............................................................................................................................................19 Application Notes: Board Layout .............................................................................................................................31 Board Layout Considerations ................................................................................................................................31
Tables
Page
Table 1. MII/5-Bit Serial Interface Signals................................................................................................................. 6 Table 2. MII Management Signals ............................................................................................................................ 7 Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Signals..................................................................................... 7 Table 4. Status Signals .............................................................................................................................................8 Table 5. Clock and Reset Signals ............................................................................................................................. 9 Table 6. Control/Status Signals ..............................................................................................................................10 Table 7. Testability Signals......................................................................................................................................12 Table 8. MII Management Frame Format................................................................................................................13 Table 9. MII Management Frames--Field Description............................................................................................13 Table 10. Absolute Maximum Ratings ....................................................................................................................14 Table 11. Operating Conditions ..............................................................................................................................14 Table 12. Summary of Management Registers (MR) .............................................................................................19 Table 13. MR0--Control Register Bit Descriptions .................................................................................................20 Table 14. MR1--Status Register Bit Descriptions ..................................................................................................21 Table 15. MR2, MR3--PHY Identification Registers (1 and 2) Bit Descriptions .....................................................22 Table 16. MR4--Autonegotiation Advertisement Register Bit Descriptions............................................................22 Table 17. MR5--Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................23 Table 18. MR5--Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions .........................23 Table 19. MR6--Autonegotiation Expansion Register Bit Descriptions..................................................................24 Table 20. MR7--Next Page Transmit Register Bit Descriptions..............................................................................25 Table 21. MR16--PCS Control Register Bit Descriptions.......................................................................................25 Table 22. MR17--Autonegotiation Read Register A...............................................................................................26 Table 23. MR18--Autonegotiation Read Register B...............................................................................................26 Table 24. MR20--User-Defined Register ...............................................................................................................27 Table 25. MR21--RXER Counter ...........................................................................................................................27 Table 26. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions ...................................................27
Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Table of Contents (continued)
Tables (continued) Page
Table 27. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions.............................................28 Table 28. MR30--Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions...............................................29 Table 29. MR31--Device-Specific Register 4 (Quick Status) Bit Descriptions .......................................................30
Figures
Page
Figure 1. DNC3X3125 Functional Block Diagram ....................................................................................................4 Figure 2. I/Os of the DNC3X3125 Macrocell ............................................................................................................5 Figure 3. DNC MII Tx Logic ....................................................................................................................................15 Figure 4. DNC MII Rx Logic....................................................................................................................................15 Figure 5. DNC Maintenance Logic .........................................................................................................................15 Figure 6. Pinout Assignment ..................................................................................................................................16 Figure 7. Typical Application ...................................................................................................................................17 Figure 8. Typical Single-Channel Twisted-Pair (TP) Interface.................................................................................18
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Description
The DNC3X3125 is a twisted-pair transceiver macrocell that supports transmission and reception over category 3 unshielded twisted-pair (UTP) cable and category 5 UTP . The DNC3X3125 has been designed specifically for applications that support both 10Base-T and 100Base-X, such as network interface cards (NICs), switches. Figure 1 represents a functional block diagram of the DNC3X3125 macrocell. Figure 2 shows the I/Os of the DNC3X3125 macrocell.
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Functional Block Diagram
100 Mbits/s TRANSCEIVER MTXD[3:0] PDT SCRAMBLER PMD TX
4B/5B ENCODER
FAR-END FAULT GEN.
MCRS MCOL MRXD[3:0] MRX_DV MRX_ER MRXCLK MTXCLK MTXD[3:0] MTX_EN MTX_ER
TX STATE MACHINE
SD COLLISION SD DETECT
RX STATE MACHINE
SD
TPO
MII INTERFACE
MII
CAR_STAT CIM RXERR_ST CARRIER DETECT ALIGNER DESCRAMBLER PDR/ DCRU SD PMD RX
5B/4B DECODER FAR-END FAULT DETECT
TPI SERIAL/PARALLEL INTERFACE CLK20 LC10 LS10 MANAGEMENT INTERFACE MDC MDIO 10 Mbits/s TRANSCEIVER LC100 LS100
MII MANAGEMENT 25 MHz
AUTONEGOTIATION AND LINK MONITOR
RMCLK 125 MHZ
FREQ. SYNTH.
125 MHz 20 MHz
25 MHz CRYSTAL
5-5136(F).j
Figure 1. DNC3X3125 Functional Block Diagram
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Description (continued)
Macrocell I/Os
APFE_PIN AUTO_EN CARIN_IN CRS_SEL EDBT ELLE_PIN EN_NOWIRE EN_RMCK EN_XTL FASTSEL[1:0] FASTTEST FX_MODE F_DUP HBT_PIN HWRESET IN125 INT_MASK ISOLATE LED_STR_EN LED_BLINK_EN LITF_ENH LPBK_PIN MDC MDIO_IN MGT_ADD[4:0] MODEL[5:0] MTXD[3:0] MTX_EN MTX_ER NOLP_PIN OUI[24:3] POR PWRDN RMCLK SDBT SDFX SECUR SER_SEL_PIN SPEED_PIN TESTMDC TESTMDIN TESTSEL[3:0] TESTTXD[3:0] TESTTXEN TESTTXER TPI TPIB VERSION[3:0] XLO BYPPD125 BYPPD160 CK125_BUF
ATBON ATBOP AUTODONE CLK25RAW CS ECLN ECLP FDUP_OUT INT_R31 LS100_OK LS10_OK LS_OK MCOL MCRS MDIO_HI_Z MDIO_OUT MRXCLK MRXD[3:0] MRX_DV MRX_ER MTXCLK REG20_OUT[15:0] REXT10 REXT100 REXTBS RMCLKRAW RS RST_10_BUSY RST_BUSY RST_TX_BUSY SERIAL_SEL SLOWCLK TESTCOL TESTCRS TESTMDHZ TESTMDOUT TESTRXCK TESTRXDV TESTRXD[3:0] TESTRXER TESTTXCK TPAPS TPJS TPO TPOB XHI XS CK125P CK160
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DNC3X3125
5-7541(F).r4
Figure 2. I/Os of the DNC3X3125 Macrocell
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Signal Information
Signal Descriptions
Table 1. MII/5-Bit Serial Interface Signals Signal MCOL Type O Name/Description Collision Detect. This signal signifies in half-duplex mode that a collision has occurred on the network. MCOL is asserted high whenever there is transmit and receive activity on the UTP media. MCOL is the logical AND of MTX_EN and receive activity, and is an asynchronous output. When SER_SEL_PIN is high and in 10Base-T mode, MCOL indicates the jabber timer has expired. Carrier Sense. When CRS_SEL is low, this signal is asserted high when either the transmit or receive medium is nonidle. This signal remains asserted throughout a collision condition. When CRS_SEL is high, MCRS is asserted on receive activity only. CRS_SEL is set via the MII management interface or the CRS_SEL signal. Receive Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s nibble mode, and 10 MHz in 10 Mbits/s serial mode. MRXCLK has a worst-case 35/65 duty cycle. MRXCLK provides the timing reference for the transfer of MRX_DV, MRXD, and MRX_ER signals. Receive Data. 4-bit parallel data outputs that are synchronous to MRXCLK. When MRX_ER is asserted high in 100 Mbits/s mode, an error code will be presented on MRXD[3:0] where appropriate. The codes are as follows: Packet errors: ERROR_CODES = 2h. Link errors: ERROR_CODES = 3h. (Packet and link error codes will only be repeated if registers [29.9] and [29.8] are enabled.) Premature end errors: ERROR_CODES = 4h. Code errors: ERROR_CODES = 5h. When SER_SEL_PIN is active-high and 10 Mbits/s mode is selected, MRXD[0] is used for data output and MRXD[3:1] are 3-stated. Receive Data Valid. When this signal is high, it indicates the DNC3X3125 is recovering and decoding valid nibbles on MRXD[3:0], and the data is synchronous with MRXCLK. MRX_DV is synchronous with MRXCLK. This signal is not used in serial 10 Mbits/s mode. Receive Error. When high, MRX_ER indicates the DNC3X3125 has detected a coding error in the frame presently being received. MRX_ER is synchronous with MRXCLK. When the encoder/decoder bypass (EDBT) is selected through the MII management interface, this output serves as the MRXD[4] output. Transmit Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s MII mode, 10 MHz output in 10 Mbits/s serial mode. MTXCLK provides timing reference for the transfer of the MTX_EN, MTXD, and MTX_ER signals sampled on the rising edge of MTXCLK. Transmit Data. 4-bit parallel input synchronous with MTXCLK. When SER_SEL_PIN is active-high and 10 Mbits/s mode is selected, only MTXD[0] is valid. Transmit Enable. When driven high, this signal indicates there is valid data on MTXD[3:0]. MTX_EN is synchronous with MTXCLK. When SER_SEL_PIN is active-high and 10 Mbits/s mode is selected, this signal indicates there is valid data on MTXD[0]. Transmit Coding Error. When driven high, this signal causes the encoder to intentionally corrupt the byte being transmitted across the MII (00100 will be transmitted). When the encoder/decoder bypass bit is set, this input serves as the MTXD[4] input. When in 10 Mbits/s mode, this signal is ignored.
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MCRS
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MRXCLK
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MRXD[3:0]
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MRX_DV
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MRX_ER
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MTXCLK
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MTXD[3:0] MTX_EN
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MTX_ER
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Signal Information (continued)
Table 2. MII Management Signals Signal MDC Type I Name/Description Management Data Clock. This is the timing reference for the transfer of data on the MDIO signal. This signal may be asynchronous to MRXCLK and MTXCLK. The maximum clock rate is 12.5 MHz. When running MDC above 6.25 MHz, MDC must be synchronous with CLK25RAW and have a setup time of 15 ns and a hold time of 5 ns with respect to CLK25RAW. Management Data Input. Control information is driven by the station management, synchronous with MDC, onto this input. Management Data Output. Status information is driven by the DNC3X3125, synchronous with MDC, onto this output. Management Data Output Enable. When high, this signal can be used to 3-state the MDIO bidirectional buffer (external to the DNC3X3125). Interrupt Mask. When set high, no interrupt is generated under any condition. When set low, interrupts are generated according to bit [31.7]. This signal is ORed with bit [31.6]. Maskable Status Interrupt. This signal will go high whenever there is a change in status as defined in Table 27.
MDIO_IN MDIO_OUT MDIO_HI_Z INT_MASK
I O O I
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INT_R31
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Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Signals Signal TPI Type PADI Name/Description Received Data. Positive differential received 125 Mbaud MLT3 or 10 Mbaud Manchester data from magnetics. Fiber-Optic Data Input. Positive differential received 125 Mbaud pseudo-ECL data from fiber transceiver. Received Data. Negative differential received 125 Mbaud MLT3 or 10 Mbaud Manchester data from magnetics. Fiber-Optic Data Input. Negative differential received 125 Mbaud pseudo-ECL data from fiber transceiver. Transmit Data. Positive differential transmit 125 Mbaud MLT3 or 10 Mbaud Manchester data to magnetics. Fiber-Optic Data Output. Positive differential transmit 125 Mbaud pseudo-ECL compatible data to fiber transceiver. Transmit Data. Negative differential transmit 125 Mbaud MLT3 or 10 Mbaud Manchester data to magnetics. Fiber-Optic Data Output. Negative differential transmit 125 Mbaud pseudoECL compatible data to fiber transceiver. Current Setting 10 Mbits/s. An external resistor (21.0 k) is placed from this signal to ground to set the 10 Mbits/s TP driver transmit output level. Current Setting 100 Mbits/s. An external resistor (21.5 k) is placed from this signal to ground to set the 100 Mbits/s TP driver transmit output level. Band Gap Reference for the Receive Channel. Connect this signal to a 24.9 k 1% resistor to ground. The parasitic load capacitance should be less than 15 pF.
TPIB
PADI
TPO
PADO
TPOB
PADO
REXT10 REXT100 REXTBS
PADO PADO PADO
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Signal Information (continued)
LEDs operate as follows: LED_STR_EN = 0, LED_BLINK_EN = 0 => No stretching/blinking. LED_STR_EN = 1, LED_BLINK_EN = 0 => Stretch to 42 ms, minimum. LED_STR_EN = 0, LED_BLINK_EN = 1 => Every activity causes 42 mS ON, 42 mS OFF blink. LED_STR_EN = 1, LED_BLINK_EN = 1 => Every activity causes 0.5 second ON, 0.5 second OFF blink. Table 4. Status Signals Signal Type O O O O O O O O O Name/Description Transmit Status. This signal indicates transmit activity. This output can be stretched or blinked per the description given above. Receive Status. This signal indicates receive activity. This output can be stretched or blinked per the description given above. Collision Status. This signal indicates collision occurrence. This output can be stretched or blinked per the description given above. Link10. This signal indicates good link status for 10 Mbits/s. Link100. This signal indicates good link status for 100 Mbits/s. Link Status. Indicates link status. Full-Duplex Status. If this signal is high, it indicates full-duplex link, and if it is low, then the link is half duplex. Jabber Status. Indicates that there is a jabber condition (only in 10 Mbits/s). TP Autopolarity Status. Indicates if autopolarity has been detected and corrected.
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XS RS CS LS10_OK LS100_OK LS_OK FDUP_OUT TPJS TPAPS
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Signal Information (continued)
Table 5. Clock and Reset Signals Signal EN_RMCK RMCLK Type I PADI* Name/Description Enable RMCLK. When high, this signal selects RMCLK as the clock input. This signal and EN_XTL cannot be high simultaneously. Primary Input Clock. The frequency of this clock can be either 125 MHz or 50 MHz. IN125 is used to indicate the appropriate frequency. This clock input is used when EN_RMCK is high. Input Clock Frequency Select. When high, this signal will indicate that the frequency of RMCLK is 125 MHz; else the clock frequency is 50 MHz. Enable Crystal Input. This signal, when high, will select the crystal input (XLO) as the clock input. This signal and EN_RMCK cannot be high simultaneously. Enable Nowire Mode. When high, this signal enables NOWIRE logic, which causes the chip to go into an ultra-low power mode when there is no signalling from the PHY at the far end of the link. Crystal Oscillator Input. A 25 MHz crystal 25 ppm can be connected across XLO and XHI. Alternately, a 25 MHz external CMOS oscillator can be connected to this input. This clock input is used when EN_XTL is high. Crystal Oscillator Output. This pad does not have to be bonded out if crystal is not used. CLK25RAW. 25 MHz output clock. RMCLKRAW. Buffered version of the RMCLK. This is either 50 MHz or 125 MHz, depending on RMCLK frequency. 24 Hz Clock Output. This is a 24 Hz output signal. Full-Chip Reset. Reset is active-high. The RST_BUSY signal will go low when reset is complete. 10Base-T and 100Base-TX/-FX are in reset until enabled and take 1.3 ms to come out of reset. The HWRESET should be a minimum of 40 nS wide. Power-On Reset. If a powerup reset (PUR) cell from ASIC library is not used, then tie this input low. Reset Busy. This signal indicates that the DNC3X3125 is in reset. 10Base-T in Reset. This signal indicates that the 10 Mbits/s logic is in reset. 100Base-TX Reset. This signal indicates that the 100 Mbits/s logic is in reset. This pin, when high, powers up the 125 MHz PLL permanently, allowing CK125P to be used for external logic at all times. This pin, when high, powers up the 160 MHz PLL permanently, allowing CK160 to be used for external logic at all times. This pin is the feedback for CK125P Normally this will be connected to . CK125P or any external chip clock buffers for CK125P . This is a 160 MHz output clock; this will be available if 10Base-T is enabled or BYPPD160 is high. This is a 125 MHz output clock, which must be fed back to CK125_BUF. This will be available when in 100Base-Tx mode or if BYPPD125 is high or if IN125 is high.
IN125 EN_XTL
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EN_NOWR
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XLO
PADI
XHI CLK25RAW RMCLKRAW SLOWCLK HWRESET
PADO (optional) O O O I
POR RST_BUSY RST_10_BUSY RST_TX_BUSY BYPPD125 BYPPD160 CK125_BUF CK160 CK125P
I O O O I I I O O
* Double bonded with XLO. Double bonded with RMCLK.
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Signal Information (continued)
Table 6. Control/Status Signals Signal AUTO_EN Type I Description Autonegotiation Enable. When this signal is high, autonegotiation is enabled. Pulsing this signal will cause autonegotiation to restart. This input has the same function as register 0, bit 12. This input and the register bit are ANDed together. Full-Duplex Mode. When this signal is set high, the PHY will be in fullduplex mode. A low on this signal will put it in half-duplex mode. This signal is ignored when autonegotiation is enabled. This is the same function as register 0, bit 8. This input and the register bit are ORed together. Carrier Sense Select. This signal may be used to select the mode of MCRS operation. When this signal is pulled high, MCRS will be asserted on receive activity only. This is the same function as register 29, bit 10. This input and the register bit are ORed together. Serial Mode Select. This signal may be used to set the SERIAL_SEL function of register 30, bit 1 by pulling it high, if station management is unavailable. This input and the register bit are ORed together. Carrier Integrity Enable. If this signal is pulled high, it will enable the carrier integrity function of register 29, bit 3, if station management is unavailable. This input and the register bit are ORed together. Encoder/Decoder Bypass. If this signal is pulled high, it will enable the encoder/decoder bypass function of register 29, bit 6, if station management is unavailable. This input and the register bit are ORed together. Scrambler/Descrambler. This signal may be used to enable the scrambler/ descrambler bypass function by pulling this signal high, if station management is unavailable. This is the same function as register 29, bit 4. This input and the register bit are ORed together. Speed. This signal can be used to select the operating speed and is the same function as register 0, bit 13:
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F_DUP
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CRS_SEL I
SER_SEL_PIN
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CARIN_IN
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EDBT
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SDBT
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SPEED_PIN
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If this signal is pulled high, it will enable 100 Mbits/s operation. If this signal is pulled low, it will enable 10 Mbits/s operation.
MGT_ADD[4:0] FX_MODE FASTTEST
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FASTSEL[1:0]
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LITF_ENH
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This signal is ignored when autonegotiation is enabled. This signal and the register bit are ANDed. Management Address [4:0]. These signals are used to set the MGT address. Management address 00000 is not a broadcast address. FX_MODE. When this signal is high, it puts DNC3X3125 in fiber-optic mode. This signal is ORed with register 29, bit 0 [29.0]. Fast Test. This signal should be low for normal operation. When high, the internal timers run faster than normal, with the speedup determined by FASTSEL[1:0] Fast Speed Select. When FASTTEST is high, the speedup of the timers (10 Mbit/s NLP link, 10 Mbit/s jabber, reset timers, autonegotiation counters) is as follows: 00 = No speedup. 01 = 16x speedup. 10 = 64x speedup. 11 = 256x speedup. (Autonegotiation does not work at this speedup.) Enhanced Link Integrity Test Function. When this input is high, The link will be deasserted when 31 Manchester violations have occurred.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Signal Information (continued)
Table 6. Control/Status Signals (continued) Signal SDFX SECUR ISOLATE Type PAD (optional I) I I Description SDFX. Signal detect from fiber-optic receiver. This pad does not have to be bonded out if fiber mode is not used. Security. When this input is high and MTX_EN is high, JAM pattern (55) is transmitted. Isolate. When this signal is high, the macrocell will come out of reset in isolate mode per the IEEE standard. If this is low, then the macrocell will come out of reset in normal mode. When isolated, all receive outputs are low, and all transmit requests are ignored. While isolated, the macrcell will respond to management transactions, detect, and transmit link pulses. Register 0, bit 10, is used to put the transceiver in/out of isolate mode. Autopolarity Function Enable (Active Low). When this signal is set low and the DNC3X3625 is operating at 10 Mbits/s, the autopolarity function will determine if the TP link is wired with a polarity reversal:
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APFE_PIN
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The DNC3X3625 will assert the autopolarity status (APS) bit (register 28, bit 6) and correct the polarity reversal.
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ELLE_PIN
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HBT_PIN
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LPBK_PIN
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NOLP_PIN
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LED_STR_EN
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LED_BLINK_EN
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OUI[24:3] MODEL[5:0] VERSION[3:0] PWRDN
I I I I
If this signal is set high and the DNC3X3625 is operating at 10 Mbits/s, the reversal will not be corrected. Extended Line Length Enable. When this signal is set high, the receive squelch level is reduced from a nominal 435 mV to 350 mV, allowing reception of signals with lower amplitude. This is the same function as register 30, bit 4. The input and the register bit are ORed together. Heartbeat Enable. When asserted high, this input will enable the heartbeat function (serial mode). This is the same function as register 30, bit 5. The input and the register bit are ORed together. Loopback. When this signal is asserted high DNC3X3125 is in loopback mode. No data transmission will take place on the media and any receive data will be ignored. This is the same function as register 0, bit 14. The input and the register bit are ORed together. No Link Pulse Mode. Setting this signal high will allow 10 Mbits/s operation with link pulses disabled. If the DNC3X3125 is configured for 100 Mbits/s operation, this signal is ignored. This is the same function as register 30, bit 0. The input and the register bit are ORed together. LED Stretch Enable. This pin when low, disables stretching. When high, the LED output is stretched to 42 ms minimum, unless LED_BLINK_EN is high. This signal is ORed with register 29, bit 7. LED Blink Enable. This pin when low, disables blinking. When high, the LED output will blink high for 42 ms and low for 42 mS whenever there is activity, unless LED_STR_EN is high, in which case the blinking is 0.5 seconds high and 0.5 seconds low. This signal is ORed with register 29, bit 11. Organizationally Unique Identifier. This can be programmed by the user, upon instantiation of the macro. Model Number. 6-bit model number of the device. This can be programmed upon instantiation. Revision Number. The value of the present revision number. This can be programmed upon instantiation. Powerdown. When high, this signal powers down the PHY. 11
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Signal Information (continued)
Table 6. Control/Status Signals (continued) Signal SERIAL_SEL Type O Description Serial Select. When this signal is high, it indicates 10 Mbit/s serial mode. When SERIAL_SEL is low, the macro is in 100 Mbits/s or 10 Mbits/s parallel mode. Autonegotiation Done. This signal goes high whenever autonegotiation has completed. It will go low if autonegotiation has to restart. Register 20 Access. This bus provides access to the user-defined register. A write to this register can be through MDIO.
AUTODONE R20_OUT[15:0]
O O
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Table 7. Testability Signals Signal TESTSEL[3:0] Type I Description Test Mode Select. These pins enable the PHY to be in various test modes: scan, analog, etc. Lucent requires access to these pins for manufacturing testing. They should be held low for normal operation. Test Mode Inputs. These test inputs provide a high level of controllability to the macrocell, either as scan inputs or as digital/analog test inputs/controls depending on the test mode selected by TESTSEL[3:0]. Test Mode Outputs. These test output pins provide observability in the form of either scan outputs or digital/analog test outputs depending on the test mode selected by TESTSEL[3:0].
TESTMDC TESTTXD[3:0] TESTTXER TESTTXEN TESTCRS TESTCOL TESTRXCK TESTTXCK TESTRXD[3:0] TESTRXER TESTRXDV ATBOP ATBON ECLP ECLN TESTMDIN TESTMDOUT TESTMDHZ
I
O
PADO (optional)
Analog Test Output Pins. These are used in Lucent test modes. They should be connected to bond pads, but are not required to be connected to package pins. Test Mode MDIN, MDOUT, and MDHZ. Input, output, and I/O control signals from/to a bidirectional buffer.
I O O
Note: All TEST I/Os are preferred to be mapped out in test mode for debug access. If the chip does not have the resources to support all I/Os, contact your Lucent representative for a list of the I/Os that are not required during test.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
MII Station Management
Basic Operation
The primary function of station management is to transfer control and status information about the DNC3X3125 to a management entity. This function is accomplished by the MDC clock input, which has a maximum frequency of 12.5 MHz, along with the MDIO signal. The MII management interface uses MDC and MDIO to physically transport information between the PHY and the station management entity. In the DNC3X3125, the MDIO pin is implemented as three signals: MDIO_IN, MDIO_OUT, and MDIO_HIZ. MDIO_IN is the information coming from the MAC and is ignored during the TA and DATA fields for MDIO reads. MDIO_HIZ will be high except during MDIO reads, in which case MDIO_OUT is the PHY data. Under no condition should the input MDIO_IN be 3-stated. These can be connected to control an I/O buffer if off-chip access is required. A specific set of registers and their contents (described in Table 9) defines the nature of the information transferred across the MDIO interface. Frames transmitted on the MII management interface will have the frame structure shown in Table 8. The order of bit transmission is from left to right. Note that reading and writing the management register must be completed without interruption. Table 8. MII Management Frame Format Read/Write (R/W) R W Pre 1. . .1 1. . .1 ST 01 01 OP 10 01 PHYAD AAAAA AAAAA REGAD RRRRR RRRRR TA Z0 10 DATA DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD IDLE Z Z
4
Table 9. MII Management Frames--Field Description Field Pre ST OP PHYADD Descriptions Preamble. The DNC3X3125 will accept frames with no preamble. This is indicated by a 1 in register 1, bit 6. Start of Frame. The start of frame is indicated by a 01 pattern. Operation Code. The operation code for a read transaction is 10. The operation code for a write transaction is a 01. PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address bit transmitted and received is the MSB of the address. A station management entity that is attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for each entity. Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY. The first register address bit transmitted and received is the MSB of the address. Turnaround. The turnaround time is a 2-bit time spacing between the register address field, and the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a write to the DNC3X3125, these bits are driven to 10 by the station. During a read, the MDIO is not driven during the first bit time and is driven to a 0 by the DNC3X3125 during the second bit time. Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register being addressed. Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be disabled and the PHY's pull-up resistor will pull the MDIO line to a logic 1.
REGAD TA
DATA IDLE
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
MII Interface Design
The chip layout will affect MII electrical specifications. Figures 3, 4, and 5 show the PHY logic on the interfaces. If the MAC logic follows the rules below, then the interface should function properly: 1. Transmit signals should change on the positive edge of TxClk. 2. Receive signals should be captured on the positive edge of RxClk. 3. Management output should change on the negative edge of MDC (and be stable on its positive edge) management inputs should be latched on the positive edge of MDC.
4
Absolute Maximum Ratings (TA = 25 C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 10. Absolute Maximum Ratings Parameter Ambient Operating Temperature Storage Temperature Power Dissipation Voltage on Any Pin with Respect to Ground Maximum Supply Voltage Symbol TA Tstg PD -- -- Min 0 -40 -- -0.5 -- Max 70 125 3.5 VDD + 0.5 3.5 Unit C C W V V
Table 11. Operating Conditions Parameter Operating Supply Voltage Power Dissipation: All Ports Autonegotiating All Ports 10Base-T Link 10Base-T TX/RX 100% 100Base-T TX Symbol -- PD PD PD PD Min -- -- -- -- -- Typ* -- 40 90 370 440 Max 3.465 50 110 400 500 Unit V mW mW mW mW
* Typical power dissipations are specified at 5 V and 25 C. This is the power dissipated by the DNC3X3125. An additional 0.2 W of power is required for the external twisted-pair driver termination resistors.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Electrical Characteristics
The following specifications apply for VDD = 3 V 5%.
MTXD MTX_ER MTX_EN TEST
TXDTX TXCLKTX MTXCLK TXCLK10 TXD10 DNC MII TX LOGIC
5-7722(F).r1
4
Figure 3. DNC MII Tx Logic
RXDTX, RXDVTX, RXERTX RXCLKTX RXER10, RXD10, RXDV10 RXCLK10 DNC MII RX LOGIC
MRXD, MRX_ER MRX_DV MRXCLK
5-7723(F).r1
Figure 4. DNC MII Rx Logic
MDIO_IN
MDIO_OUT MDIO_HI_Z
MDC
DNC MII MAINTENANCE LOGIC
5-7724(F)
Figure 5. DNC Maintenance Logic
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Electrical Characteristics (continued)
SDFX VDDA ATBOP ATBON VSSA VSSA VDDA VSS VDD VSSE ECLN ECLP VDDE
LOW-SPEED DIGITAL I/Os CAN GO HERE VSSA VDDA TPIP TPIN VSSA VDDA REXTBS VSSA VDDM VSSM VDDPD RMCLK XLO XHI VSSPD VDDA REXT100 REXT10 VSSA VSSO TPON TPOP VSSO ~2 mm TOP CORNER
LOW-SPEED DIGITAL I/Os
OPTIONAL
4
BONDED TO SAME PIN
NOTE: ANALOG POWER IS NOT CONNECTED TO CHIP DIGITAL POWER ~2 mm VSS VDD LOW-SPEED DIGITAL I/Os CAN GO HERE LOW-SPEED DIGITAL I/Os
5-7721(F).r1
Figure 6. Pinout Assignment
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Electrical Characteristics (continued)
DNC XLO RMCLK SEE APPLICATION FOR DETAILS ON EXTERNAL COMPONENTS XHI REXT10 MTXCLK REXT100 REXTBS MRXD, MRX_ER, MRX_DV RXCLK TPI RJVS TPIB TPO TPOB MDC TESTTXD TESTTXEN TESTTXER TESTCRS TESTCOL TESTTXCK TESTRXCK TESTRXD TESTRXER TESTRXDV SOME ARE OPTIONAL TESTMDIN TESTMDOUT TESTMDC MAC LOGIC TESTSEL [3:0] PHYTESTEN 1 I/O MAC LOGIC 6 TEST I/O CAN BE SHARED WITH OTHER I/Os MAC LOGIC 10 PHYTESTEN MAC LOGIC MDIO_OUT MDIO_IN MAC MANAGEMENT LOGIC MAC RX LOGIC CLK125BUF CK125P MTXD, MTX_EN, MTX_ER MAY BUFFER IF MAC USES CK125P
XLO/RMCLK BONDED TO SAME PIN
MAC TX LOGIC
4
ECLP ECLN FOR TEST SET ONLY, OPEN ON ACTUAL BOARD ATBON ATBOP
4 PHYTESTEN PHYTESTEN PHY TEST EN
5-7725(F).r1
Figure 7. Typical Application
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Electrical Characteristics (continued)
VDDO RJ-45 TPO 50 10 pF 50 TPOB 75 0.01 F TPI 6 50 7 50 TPIB 1:1 75 0.01 F 0.01 F 0.01 F 75 8 75 0.01 F 5 3 4 1:1 1 2
4
DNC3X3125
0.01 F
5-5433(F).p
Figure 8. Typical Single-Channel Twisted-Pair (TP) Interface
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information
Register Descriptions
The MII management 16-bit register set implemented is as follows. Table 12. Summary of Management Registers (MR) Register Address 0 1 2 3 4 5 6 7 8--15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR7 MR8--MR15 MR16 MR17 MR18 MR19 MR20 MR21 MR22 MR23 MR24 MR25 MR26 MR27 MR28 MR29 MR30 MR31 Name Control Status PHY Identifier 1 PHY Identifier 2 Autonegotiation Advertisement Autonegotiation Link Partner Ability Autonegotiation Expansion Next Page Transmit (Reserved) PCS Control Register Autonegotiation (read register A) Autonegotiation (read register B) Lucent Analog Test Register User-defined Register RXER Counter Lucent Analog Test Registers Default (Hex Code) 3000h 7849h TBD TBD 01E1h 0000 0000 0000 -- 0000 0000 0000 -- -- 0000 --
4
Lucent Analog Test (tuner) Registers
--
Device Specific 1 Device Specific 2 Device Specific 3 Quick Status Register
-- 2080 0000 --
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Register Information (continued)
Table 13. MR0--Control Register Bit Descriptions Bit* 0.15 (SW_RESET) 0.14 (LOOPBACK) Type R/W R/W Description Reset. Setting this bit to a 1 will reset the DNC3X3125. All registers will be set to their default state. This bit is self-clearing. The default is 0. Loopback. When this bit is set to 1, no data transmission will take place on the media. Any receive data will be ignored. The loopback signal path will contain all circuitry up to, but not including, the PMD. The default value is a 0. Speed Selection. The value of this bit reflects the current speed of operation (1 = 100 Mbits/s; 0 = 10 Mbits/s). This bit will only affect operating speed when the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is ignored when autonegotiation is enabled (register 0, bit 12). This bit is ANDed with the SPEED_PIN signal. Autonegotiation Enable. The autonegotiation process will be enabled by setting this bit to a 1. The default state is a 1. Powerdown. The DNC3X3125 may be placed in a low-power state by setting this bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver will be powered down. While in the powerdown state, the DNC3X3125 will respond to management transactions. The default state is a 0. Isolate. When this bit is set to a 1, the MII outputs will be brought to the highimpedance state. The default state is a 0. Restart Autonegotiation. Normally, the autonegotiation process is started at powerup. The process may be restarted by setting this bit to a 1. The default state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to a 1. This bit is self-cleared when autonegotiation restarts. Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 = half duplex). This bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. The default state is a 0. This bit is ORed with the F_DUP pin. Collision Test. When this bit is set to a 1, the DNC3X3125 will assert the MCOL signal in response to MTX_EN. Reserved. All bits will read 0.
0.13 (SPEED100)
R/W
4
0.12 (NWAY_ENA) 0.11 (PWRDN) R/W R/W
0.10 (ISOLATE) 0.9 (REDONWAY)
R/W R/W
0.8 (FULL_DUP)
R/W
0.7 (COLTST) 0.6:0 (RESERVED)
R/W NA
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write, NA = not applicable.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information (continued)
Table 14. MR1--Status Register Bit Descriptions Bit* 1.15 (T4ABLE) Type R Description 100Base-T4 Ability. This bit will always be a 0. 0: Not able. 1: Able. 100Base-TX Full-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 100Base-TX Half-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 10Base-T Full-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 10Base-T Half-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. Reserved. All bits will read as a 0. Suppress Preamble. When this bit is set to a 1, it indicates that the DNC3X3125 accepts management frames with the preamble suppressed. Autonegotiation Complete. When this bit is a 1, it indicates the autonegotiation process has been completed. The contents of registers MR4, MR5, MR6, and MR7 are now valid. The default value is a 0. This bit is reset when autonegotiation is started. Remote Fault. When this bit is a 1, it indicates a remote fault has been detected. This bit will remain set until cleared by reading the register. The default is a 0. Autonegotiation Ability. When this bit is a 1, it indicates the ability to perform autonegotiation. The value of this bit is always a 1. Link Status. When this bit is a 1, it indicates a valid link has been established. This bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. Jabber Detect. This bit will be a 1 whenever a jabber condition is detected. It will remain set until it is read, and the jabber condition no longer exists. Extended Capability. This bit indicates that the DNC3X3125 supports the extended register set (MR2 and beyond). It will always read a 1.
1.14 (TXFULDUP)
R
1.13 (TXHAFDUP)
R
4
1.12 (ENFULDUP)
R
1.11 (ENHAFDUP)
R
1.10:7 (RESERVED) 1.6 (NO_PA_OK) 1.5 (NWAYDONE)
R R R
1.4 (REM_FLT) 1.3 (NWAYABLE) 1.2 (LSTAT_OK)
R R R
1.1 (JABBER) 1.0 (EXT_ABLE)
R R
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read.
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Register Information (continued)
Table 15. MR2, MR3--PHY Identification Registers (1 and 2) Bit Descriptions Bit* 2.15:0 (OUI[3:18]) Type R Description Organizationally Unique Identifier. The third through the twenty-fourth bit of the OUI assigned to the PHY manufacturer by the IEEE are to be placed in bits 2.15:0 and 3.15:10. This value is programmable. Organizationally Unique Identifier. The remaining 6 bits of the OUI. The value for bits 24:19 is programmable. Model Number. 6-bit model number of the device. The model number is programmable. Revision Number. The value of the present revision number. The version number is programmable.
3.15:10 (OUI[19:24]) 3.9:4 (MODEL[5:0])
R R R
4
3.3:0 (VERSION[3:0])
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read.
Table 16. MR4--Autonegotiation Advertisement Register Bit Descriptions Bit* 4.15 (NEXT_PAGE) Type R/W Name/Description Next Page. The next page function is activated by setting this bit to a 1. This will allow the exchange of additional data. Data is carried by optional next pages of information. Acknowledge. This bit is the acknowledge bit from the link code word. Remote Fault. When set to 1, the DNC3X3125 indicates to the link partner a remote fault condition. Reserved. Pause. When set to a 1, it indicates that the DNC3X3625 wishes to exchange flow control information with its link partner. 100Base-T4. This bit should always be set to 0. 100Base-TX Full Duplex. If written to 1, autonegotiation will advertise that the DNC3X3125 is capable of 100Base-TX full-duplex operation. 100Base-TX. If written to 1, autonegotiation will advertise that the DNC3X3125 is capable of 100Base-TX operation. 10Base-T Full Duplex. If written to 1, autonegotiation will advertise that the DNC3X3125 is capable of 10Base-T full-duplex operation. 10Base-T. If written to 1, autonegotiation will advertise that the DNC3X3125 is capable of 10Base-T operation. Selector Field. Reset with the value 00001 for IEEE 802.3.
4.14 (ACK) 4.13 (REM_FAULT) 4.12:11 4.10 (PAUSE) 4.9 (100BASET4) 4.8 (100BASET_FD) 4.7 (100BASETX) 4.6 (10BASET_FD) 4.5 (10BASET) 4.4:0 (SELECT)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information (continued)
Table 17. MR5--Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions Bit* 5.15 (LP_NEXT_PAGE) 5.14 (LP_ACK) Type R R Description Link Partner Next Page. When this bit is set to 1, it indicates that the link partner wishes to engage in next page exchange. Link Partner Acknowledge. When this bit is set to 1, it indicates that the link partner has successfully received at least three consecutive and consistent FLP bursts. Remote Fault. When this bit is set to 1, it indicates that the link partner has a fault. Technology Ability Field. This field contains the technology ability of the link partner. These bits are similar to the bits defined for the MR4 register (see Table 16). Selector Field. This field contains the type of message sent by the link partner. For IEEE 802.3 compliant link partners, this field should read 00001.
5.13 (LP_REM_FAULT) 5.12:5 (LP_TECH_ABILITY)
R R
4
5.4:0 (LP_SELECT)
R
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read.
Table 18. MR5--Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions Bit* 5.15 (LP_NEXT_PAGE) 5.14 (LP_ACK) 5.13 (LP__MES_PAGE) 5.12 (LP_ACK2) Type R R R R Description Next Page. When this bit is set to a logic 0, it indicates that this is the last page to be transmitted. A logic 1 indicates that additional pages will follow. Acknowledge. When this bit is set to a logic 1, it indicates that the link partner has successfully received its partner's link code word. Message Page. This bit is used by the NEXT _PAGE function to differentiate a message page (logic 1) from an unformatted page (logic 0). Acknowledge 2. This bit is used by the NEXT_PAGE function to indicate that a device has the ability to comply with the message (logic 1) or not (logic 0). Toggle. This bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. Logic 0 indicates that the previous value of the transmitted link code word was logic 1. Logic 1 indicates that the previous value of the transmitted link code word was logic 0. Message/Unformatted Code Field. With these 11 bits, there are 2048 possible messages. Message code field definitions are described in annex 28C of the IEEE 802.3u standard.
5.11 (LP_TOGGLE)
R
5.10:0 (MCF)
R
* The format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read.
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Advance Data Sheet March 2000
Register Information (continued)
Table 19. MR6--Autonegotiation Expansion Register Bit Descriptions Bit* 6.15:5 (RESERVED) 6.4 (PAR_DET_FAULT) Type Description
4
Reserved. R R/LH Parallel Detection Fault. When this bit is set to 1, it indicates that a fault has been detected in the parallel detection function. This fault is due to more than one technology detecting concurrent link conditions. This bit can only be cleared by reading this register. Link Partner Next Page Able. When this bit is set to 1, it indicates that 6.3 (LP_NEXT_PAGE_ABLE) R the link partner supports the next page function. Next Page Able. This bit is set to 1, indicating that this device supports 6.2 (NEXT_PAGE_ABLE) R the NEXT_PAGE function. 6.1 (PAGE_REC) R/LH Page Received. When this bit is set to 1, it indicates that a NEXT_PAGE has been received. Link Partner Autonegotiation Capable. When this bit is set to 1, it indi6.0 (LP_NWAY_ABLE) R cates that the link partner is autonegotiation capable.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, LH = latched high.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information (continued)
Table 20. MR7--Next Page Transmit Register Bit Descriptions Bit* 7.15 (NEXT_PAGE) Type R/W Description Next Page. This bit indicates whether or not this is the last next page to be transmitted. When this bit is 0, it indicates that this is the last page. When this bit is 1, it indicates there is an additional next page. Acknowledge. This bit is the acknowledge bit from the link code word. Message Page. This bit is used to differentiate a message page from an unformatted page. When this bit is 0, it indicates an unformatted page. When this bit is 1, it indicates a formatted page. Acknowledge 2. This bit is used by the next page function to indicate that a device has the ability to comply with the message. It is set as follows:
s s
7.14 (ACK) 7.13 (MESSAGE)
R R/W
7.12 (ACK2)
R/W
4
When this bit is 0, it indicates the device cannot comply with the message.
7.11 (TOGGLE)
R
When this bit is 1, it indicates the device will comply with the message. Toggle. This bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange.This bit will always take the opposite value of the toggle bit in the previously exchanged link code word: s If the bit is a logic 0, the previous value of the transmitted link code word was a logic 1.
s
If the bit is a 1, the previous value of the transmitted link code word was a 0.
7.10:0 (MCF)
R/W
The initial value of the toggle bit in the first next page transmitted is the inverse of the value of bit 11 in the base link code word, and may assume a value of 1 or 0. Message/Unformatted Code Field. With these 11 bits, there are 2048 possible messages. Message code field definitions are described in annex 28C of the IEEE 802.3u standard.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
Table 21. MR16--PCS Control Register Bit Descriptions Bit* 16.15 (LOCKED) 16.14-12 (Reserved) 16.11 (ANA_RG21) 16.10 (LPWR_TUN) 16.9 (SMFIX_DA) 16.8 (EN_NOWR) 16.7-6 (ATST1:0) 16.5 (BYPPD125) 16.4 (BYPPD160) 16.3 (LOOPBACK) 16.2 (SCAN) 16.1 (FORCE LOOPBACK) 16.0 (SPEEDUP COUNTERS) Type R R R/W R/W R/W Description Locked. Locked pin from descrambler block. Reserved. Should be written as 0. Analog Regiser 21. Lucent Debug Register - Should be wrtten as 0. Low Power Tuner. Lucent Debug Register - Should be wrtten as 0. State Machine Fix. Lucent Debug Register - Should be written as 0. Enable Nowire. This bit is OR'd with EN_NOWR input Autonegotiation Testmode (1:0). Lucent Debug Register - Should be written 0 Bypass Powerdown 125. OR'd with BYPPD125 Input Bypass Powerdown 160. OR'd with BYPPD160 Input Loopback Configure. When this bit is high, the entire loopback is performed in the PCS macro. When this bit is low, only the collision pin is disabled in loopback. Scan Test Mode. Lucent Debug Register - should be written as 0. Force Loopback. Force a loopback without forcing idle on the transmit side or disabling the collision pin. Speedup Counters. Reduce link monitor counter to 10 s from 620 s. (Same as FASTTEST = 1.)
R/W R/W R/W R/W
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Register Information (continued)
Table 22. MR17--Autonegotiation Read Register A Bit* 17.15-13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Type R R R R R R R R R R R R R R Description Reserved. Always 0. Next Page Wait. Wait Link_Fail_Inhibit_Wait_Timer (Link Status Check). Wait Autoneg_Wait_Timer (Link Status Check). Wait Break_Link_Timer (Transmit Disable). Parallel Detection Fault. Autonegotiation Enable. FLP Link Good Check. Complete Acknowledge. Acknowledge Detect. FLP Link Good. Link Status Check. Ability Detect. Transmit Disable.
4
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
Table 23. MR18--Autonegotiation Read Register B Bit* 18.15 18.14 18.13 18.12 18.11 18.10 18.9 18.8 18.7 18.6 18.5 18.4 18.3 18.2 18.1 18.0 Type R R R R R R R R R R R R R R R R Description Receiving FLPs. Any of FLP Capture, Clock, Data_0, or Data_1 (FLP Rcv). FLP Pass (FLP Rcv). Link Pulse Count (FLP Rcv). Link Pulse Detect (FLP Rcv). Test Pass (NLP Rcv). Test Fail Count (NLP Rcv). Test Fail Extend (NLP Rcv). Wait Max Timer Ack (NLP Rcv). Detect Freeze (NLP Rcv). Test Fail (NLP Rcv). Transmit Count Ack (FLP Xmit). Transmit Data Bit (FLP Xmit). Transmit Clock Bit (FLP Xmit). Transmit ability (FLP Xmit). Transmit Remaining Acknowledge (FLP Xmit). Idle (FLP Xmit).
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information (continued)
Table 24. MR20--User-Defined Register Bit* 20.[15:0] Type R/W Description The data written into this user-defined register appears on the R20_OUT[15:0] bus.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
Table 25. MR21--RXER Counter Bit* 21.0 21.15:0 21.7:0 21.11:8 21.15:12 Type W R R R R Description This bit, when 0 puts this register in 16-bit counter mode. When 1, it puts this register in 8-bit counter mode. This bit is reset to a 0 and cannot be read. When in 16-bit counter mode, these maintain a count of RXERs. It is reset on a read operation. When in 8-bit counter mode, these maintain a count of RXERs. It is reset on a read operation When in 8-bit mode, these contain a count of false carrier events (802.3 section 27.3.1.5.1). It is reset on a read operaton. When in 8-bit mode, these contain a count of disconnect events (Link Unstable 6, 802.3 section 27.3.1.5.1). It is reset on a read operation.
4
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
Table 26. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions Bit* 28.15:9 (UNUSED) 28.8 (BAD_FRM) Type R R/LH Description Unused. Read as 0. Bad Frame. If this bit is a 1, it indicates a packet has been received without an SFD. This bit is only valid in 10 Mbits/s mode. This bit is latching high and will only clear after it has been read or the device has been reset. Code Violation. When this bit is a 1, it indicates a Manchester code violation has occurred. The error code will be output on the MRXD lines. Refer to Table 1 for a detailed description of the MRXD pin error codes. This bit is only valid in 10 Mbits/s mode. This bit is latching high and will only clear after it has been read or the device has been reset. Autopolarity Status. When register 30, bit 3 is set and this bit is a 1, it indicates the DNC3X3125 has detected and corrected a polarity reversal on the twisted pair. If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside the DNC3X3125. This bit is not valid in 100 Mbits/s operation. Disconnect. If this bit is a 1, it indicates a disconnect. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. Unlocked. Indicates that the TX scrambler lost lock. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. RX Error Status. Indicates a false carrier. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode.
28.7 (CODE)
R/LH
28.6 (APS)
R
28.5 (DISCON) 28.4 (UNLOCKED) 28.3 (RXERR_ST)
R/LH R/LH R/LH
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Register Information (continued)
Table 26. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions (continued) Bit* 28.2 (FRC_JAM) 28.1 (LNK100UP) 28.0 (LNK10UP) Type R/LH R R Description Force Jam. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. Link Up 100. This bit, when set to a 1, indicates a 100 Mbits/s transceiver is up and operational. Link Up 10. This bit, when set to a 1, indicates a 10 Mbits/s transceiver is up and operational.
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* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, LH = latched high.
Table 27. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions Bit* 29.15 (LOCALRST) Type R/W Description Management Reset. This is the local management reset bit. Writing a logic 1 to this bit will cause the lower 16 registers and registers 28 and 29 to be reset to their default values. This bit is self-clearing. Generic Reset 1. This register is used for manufacture test only. Generic Reset 2. This register is used for manufacture test only. 100 Mbits/s Transmitter Off. When this bit is set to 0, it forces TPI low and TPIB- high. This bit defaults to 1. LED Blinking. This register, when 1, enables LED blinking. This is ORed with LED_BLINK_EN. Default is 0. Carrier Sense Select. MCRS will be asserted on receive only when this bit is set to a 1. If this bit is set to logic 0, MCRS will by asserted on receive or transmit. This bit is ORed with the CRS_SEL pin. Link Error Indication. When this bit is a 1, a link error code will be reported on MRXD[3:0] of the DNC3X3125 when MRX_ER is asserted on the MII. The specific error codes are listed in the MRXD pin description. If it is 0, it will disable this function. Packet Error Indication Enable. When this bit is a 1, a packet error code, which indicates that the scrambler is not locked, will be reported on MRXD[3:0] of the DNC3X3125 when MRX_ER is asserted on the MII. When this bit is 0, it will disable this function. Pulse Stretching. When this bit is set to 1, the CS, XS, and RS output signals will be stretched between approximately 42 ms--84 ms. If this bit is 0, it will disable this feature. Default state is 0. Encoder/Decoder Bypass. When this bit is set to 1, the 4B/5B encoder and 5B/4B decoder function will be disabled. This bit is ORed with the EDBT pin. Symbol Aligner Bypass. When this bit is set to 1, the aligner function will be disabled. Scrambler/Descrambler Bypass. When this bit is set to 1, the scrambling/ descrambling functions will be disabled. This bit is ORed with the SDBT pin. Carrier Integrity Enable. When this bit is set to a 1, carrier integrity is enabled. This bit is ORed with the CARIN_EN pin. Jam Enable. When this bit is a 1, it enables JAM associated with carrier integrity to be ORed with MCOLMCRS.
29.14 (RST1) 29.13 (RST2) 29.12 (100_OFF) 29.11 (LED_BLINK 29.10 (CRS_SEL)
R/W R/W R/W R/W R/W
29.9 (LINK_ERR)
R/W
29.8 (PKT_ERR)
R/W
29.7 (PULSE_STR)
R/W
29.6 (EDB) 29.5 (SAB) 29.4 (SDB) 29.3 (CARIN_EN) 29.2 (JAM_COL)
R/W R/W R/W R/W R/W
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information (continued)
Table 27. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions (continued) Bit* 29.1 (FEF-EN) Type R/W Description Far-End Fault Enable. This bit is used to enable the far-end fault detection and transmission capability. This capability may only be used if autonegotiation is disabled. This capability is to be used only with media which does not support autonegotiation. Setting this bit to 1 enables far-end fault detection, and logic 0 will disable the function. Default state is 0. Fiber-Optic Mode. When this bit is a 1, the DNC3X3125 is in fiber-optic mode. This bit is ORed with FX_MODE.
29.0 (FX)
R/W
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
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Table 28. MR30--Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions Bit* 30.15 (Test10TX) 30.14 (RxPLLEn) Type R/W R/W Description When high and 10Base-T is powered up, a continuous 10 MHz signal (1111) will be transmitted. This is only meant for testing. Default 0. When high, all 10Base-T logic will be powered up when the link is up. Otherwise, portions of the logic will be powered down when no data is being received to conserve power. Default is 0. Jabber Disable. When this bit is 1, disables the jabber function of the 10Base-T receive. Default is 0. Reserved. Should be written as 0. Enhanced Link Integrity Test Function. When high, function is enabled. This is ORed with the LITF_ENH input. Default is 0. Heartbeat Enable. When this bit is a 1, the heartbeat function will be enabled. Valid in 10 Mbits/s mode only. Extended Line Length Enable. When this bit is a 1, the receive squelch levels are reduced from a nominal 435 mV to 350 mV, allowing reception of signals with a lower amplitude. Valid in 10 Mbits/s mode only. Autopolarity Function Disable. When this bit is a 0 and the DNC3X3125 is in 10 Mbits/s mode, the autopolarity function will determine if the TP link is wired with a polarity reversal. If there is a polarity reversal, the DNC3X3125 will assert the APS bit (register 28, bit 6) and correct the polarity reversal. If this bit is a 1 and the device is in 10 Mbits/s mode, the reversal will not be corrected. Reserved. Should be written as 0. Serial Select. When this bit is set to a 1, 10 Mbits/s serial mode will be selected. When the DNC3X3125 is in 100 Mbits/s mode, this bit will be ignored. No Link Pulse Mode. Setting this bit to a 1 will allow 10 Mbits/s operation with link pulses disabled. If the DNC3X3125 is configured for 100 Mbits/s operation, setting this bit will not affect operation.
30.13 (JAB_DIS) 30.12:7 (Reserved) 30.6 (LITF_ENH) 30.5 (HBT_EN) 30.4 (ELL_EN)
R/W R/W R/W R/W R/W
30.3 (APF_EN)
R/W
30.2 (RESERVED) 30.1 (SERIAL _SEL)
R/W R/W
30.0 (ENA_NO_LP)
R/W
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register. R = read, W = write.
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DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Register Information (continued)
Table 29. MR31--Device-Specific Register 4 (Quick Status) Bit Descriptions
Register/Bit1 31.15 (ERROR) Type2 R Description Receiver Error. When this bit is a 1, it indicates that a receive error has been detected. This bit is valid in 100 Mbits/s only. This bit will remain set until cleared by reading the register. Default is a 0. False Carrier. When bit [31.7] is set to 0 and this bit is a 1, it indicates that the carrier detect state machine has found a false carrier. This bit is valid in 100 Mbits/s only. This bit will remain set until cleared by reading the register. Default is 0. Link Status Change. When bit [31.7] is set to a 1, this bit is redefined to become the LINK_STAT_CHANGE bit and goes high whenever there is a change in link status (bit [31.11] changes state). Remote Fault. When this bit is a 1, it indicates a remote fault has been detected. This bit will remain set until cleared by reading the register. Default is a 0. Unlocked/Jabber. If this bit is set when operating in 100 Mbits/s mode, it indicates that the TX descrambler has lost lock. If this bit is set when operating in 10 Mbits/s mode, it indicates a jabber condition has been detected. This bit will remain set until cleared by reading the register. Link Status. When this bit is a 1, it indicates a valid link has been established. This bit has a latching low function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. Link Partner Pause. When this bit is set to a 1, it indicates that the DNC3X3125 wishes to exchange flow control information. Link Speed. When this bit is set to a 1, it indicates that the link has negotiated to 100 Mbits/s. When this bit is a 0, it indicates that the link is operating at 10 Mbits/s. Duplex Mode. When this bit is set to a 1, it indicates that the link has negotiated to full-duplex mode. When this bit is a 0, it indicates that the link has negotiated to halfduplex mode. Interrupt Configuration. When this bit is set to a 0, it defines bit [31.14] to be the RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high whenever any of bits [31.15:12] go high, or bit [31.11] goes low. When this bit is set high, it redefines bit [31.14] to become the LINK_STAT_CHANGE bit, and the interrupt pin (MASK_STAT_INT) goes high only when the link status changes (bit [31.14] goes high). This bit defaults to 0. Interrupt Mask. When set high, no interrupt is generated by this channel under any condition. When set low, interrupts are generated according to bit [31.7]. Lowest Autonegotiation State. These 3 bits report the state of the lowest autonegotiation state reached since the last register read, in the priority order defined below: 000: Autonegotiation enable. 001: Transmit disable or ability detect. 010: Link status check. 011: Acknowledge detect. 100: Complete acknowledge. 101: FLP link good check. 110: Next page wait. 111: FLP link good. Highest Autonegotiation State. These 3 bits report the state of the highest autonegotiation state reached since the last register read, as defined above for bit [31.5:3].
31.14 (RXERR_ST)/ (LINK_STAT_CHANGE)
R
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31.13 (REM_FLT) 31.12 (UNLOCKED)/ (JABBER) R R
31.11 (LSTAT_OK)
R
31.10 (PAUSE) 31.9 (SPEED100) 31.8 (FULL_DUP)
R R R
31.7 (INT_CONF)
R/W
31.6 (INT_MASK) 31.5:3 (LOW_AUTO__STATE)
R/W R
31.2:0 (HI_AUTO_STATE)
R
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2 R = read; W = write.
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Advance Data Sheet March 2000
DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
each power pin and the ground plane are required. This can be achieved by using short traces to the power pins and connecting to the ground plane with two vias. Multilayer ceramic capacitors with good quality dielectric such as NPO or X7R (avoid using Z5U) are recommended for the low ESR capacitors. A 0.01 F capacitor should be used on every pin, for conservative designs two capacitors can be used on every pin a 0.1 F and a 0.001 F. 5. Route the transmit and receive pairs between the ASIC, the magnetics, and the RJ-45 connectors as short, straight, and equal length as possible. These traces should be routed with 50 impedance to the nearest power/ground plane with a differential impedance of 100 . Keep the separation between adjacent pairs on the same layer, 2 mm or more if possible to minimize crosstalk. 6. The most EMI critical routing is between the magnetic module (after common-mode filters) and the RJ-45 connectors. Use the chassis of the system to allow coupled noise to flow to ground via common mode terminations. The chassis is not a perfect ground, but with proper power supply design, the chassis can be used to redirect some commonmode noise. 7. Reduce the number of vias on the transmit path. Vias can have resonance at critical frequencies degrading EMI emissions performance. The transmit differential pairs from the RJ-45 to the magnetics and the DNC3X3125 can be run on the top layer of the board. Vias on the receive path should be minimized but are less critical because the signal energy is less than on the transmit path. The receive signals can be run on a buried layer or on the bottom layer. 8. Ensure that the 25 MHz crystal and the load capacitors (33 pF), or the oscillator (25 MHz,50 MHz, or 125 MHz if used), are located as close to the XLO/ XHI pins as possible. All bias resistors (pins 13, 25, 42, and 43) and reference capacitor (pin 81) must be located within close proximity to the PHY. This will reduce the coupled noise into the bias circuits. Place receive twisted-pair terminating resistors (100 ) as close to PHY pins as possible. 9. Never route clock or high-speed signal lines under the ASIC unless the lines are under a ground or power plane.
Application Notes: Board Layout
Board Layout Considerations
In order to obtain optimum performance, careful attention must be paid to the circuit board layout, shielding, and the placement of components. Careful routing of high-speed lines is mandatory. Power supply input pins must be protected from noisy conditions by proper filtering. To achieve these design goals, the following steps are recommended as a minimum. 1. As a minimum, a four-layer circuit board, with twoounce copper planes, should be used. This will minimize the switching transients by providing a lowimpedance power source. The signal planes should be isolated from each other by the power and/or ground planes. Do not segment the ground plane except around the RJ-45 connectors and magnetics module as described below. Use a single, continuous plane. The reference design will be a six-layer board. 2. Power and ground planes should extend underneath the ASIC up to the input of the magnetic module. Power and ground planes should not extend under any network signal path, or the magnetics module, because common-mode power supply noise, will be coupled to the signals. The greater the distance between the planes and the network signals, the lower the EMI emissions. Chassis ground may be used under the RJ-45 connectors if desired. 3. The power plane of the ASIC should be separated into three regions: digital power (VDDD this is the PWB's VDD plane), analog power (VDDA), and output driver power (VDDO). For conservative designs, the VDDA segment and the VDDO segment, should be filtered with a ferrite bead, 10 F, and 0.01 F capacitors before connecting to the VDD plane with a heavy wide trace. Pins 80 VDDPLL and 83 VDDPD can be connected together and filtered with a ferrite bead and 10 F and 0.01 F capacitors for conservative designs. Refer to Figure 3 for suggested layout. Do not overlay different power planes on different layers, unless they are separated by a ground plane. When segmenting power planes on the same layer, they should be separated by at least three times the distance to the nearest ground layer. 4. The liberal use of capacitors on each the power pins of the ASIC will minimize any noise coupled into the power plane. Power supply noise contributes to the EMI emissions in circuit layouts. Low ESR capacitors between the power and ground planes must be placed as close as possible to all the DNC3X3125 power pins. Low-inductance short connections to
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For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
March 2000 DS00-079LAN (Replaces DS99-161LAN)

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